1. Field of Invention
The present invention relates to a method of testing reliability of a semiconductor device and circuit, and particularly to a method of performing a non-destructive rapid test on negative bias temperature instability (NBTI) of a pMOSFET.
2. Description of Prior Art
Reliability testing of the semiconductor device is a key technical issue in the field of integrated circuit technology. Negative bias temperature instability (NBTI) of the p-type field effect transistor (pMOSFET) in CMOS circuits is one of the main reliability concern in the current semiconductor technology, which indicates the degradation of pMOSFET characteristics under negative gate voltage and temperature stress, such as increase in threshold voltage Vth and reduction in drain current Id. NBTI induces continuous performance degradation of pMOS transistors with stress time, and ultimately makes the failure of device and even circuit.
The aggressive scaling down of MOSFETs integrated circuit technology requires the continuous reduction of gate oxide dielectric thickness. Although the wide integration of SiON gate dielectric or high-K gate dielectric in nowadays semiconductor industry has effectively suppressed gate leakage, it makes NBTI more significant than ever before.
A conventional NBTI testing method comprises that under a high temperature, a constant voltage stress between 8 MV/cm to 12 MV/cm which is much higher than an operating voltage may be applied to the gate electrode of a MOSFET. A stress time is generally thousands of seconds to several ten thousands of seconds and more. Then, a degradation of the electrical parameter, such as the device threshold voltage, with the stress time may be measured for a certain time interval. For example, following documents disclose conventional NBTI testing method in detail:    Document 1: US Patent Application No. 2003/0231028 A1;    Document 2: T. Grasser, P. Wagner, P. Hehenberger, W. Goes, and B. Kaczer, “A Rigorous Study of Measurement Techniques for Negative Bias Temperature Instability,” IEEE Trans. Device Mater. Rel., vol. 8, no. 3, 2008, pp. 526-535.
Consequently, the conventional NBTI testing is a time-consuming work and of a heavy workload. In addition, a serious degradation has occurred to the electrical parameters of the device sample which can not be used any more after the NBTI stress test.
Therefore, how to improve efficiency of the NBTI test and to reduce a loss rate of the test sample have important significances for the integrated circuit technology.